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w83194br - s 200mhz 2 - dimm clock for solano chipset publication release date:june 2000 - 1 - revision 0.42 1.0 general descrip tion the w83194br - s is a clock synthesizer for intel 815 solano chipset. w83194br - s provides all clocks required for high - speed risc or cisc microprocessor and also provides 64 different frequencies of cpu, sdram, pci, 3v66, ioapic clo cks frequency setting. all clocks are externally selectable with smooth transitions. the w83194br - s provides i 2 c serial bus interface to program the registers to enable or disable each clock outputs and provides 0.25% and 0.5% center type spread spectru m to reduce emi. the w83194br - s provides stepless frequency programming by controlling the vco freq. and the clock output divisor ratio. also the skew of cpu, sdram and 3v66 clock outputs are programmable. a watch dog timer is quipped and when time out, t he reset# pin will output 4ms pulse signal. the w83194br - s accepts a 14.318 mhz reference crystal as its input and runs on a 3.3v supply. high drive pci and sdram clock outputs typically provide greater than 1 v /ns slew rate into 30 pf loads. cpu clock outputs typically provide better than 1 v /ns slew rate into 20 pf loads as maintaining 50 5% duty cycle. the fixed frequency outputs as ref, 24mhz, and 48 mhz provide better than 0.5v /ns slew rate. 2.0 product feature s 2 cpu clocks 3 3v66 for chi pset and agp clocks 9 sdram clocks for 2 dimms 7 pci synchronous clocks. optional single or mixed supply: (vddr = vddp=vdds = vdd48 = vdd3 = 3.3v, vdd lapic =vdd lcpu =2.5v) skew form cpu to pci clock - 1 to 4 ns, center 2.6 ns smooth frequency switch with selections from 66.8 to 200 mhz i 2 c 2 - wire serial interface and i 2 c read back 0.25% and 0.5% center type spread spectrum programmable registers to enable/stop each output and select modes two 48 mhz pins for usb 24 mhz for super i/o 48 - pin ssop package
w83194br - s preliminary publ ication release date: june 2000 - 2 - revision 0.42 3.0 pin configurati on 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 vddr vss xin xout pciclk0^/ *fs0 vss48 pciclk6 pciclk2^/*fs2 pciclk3/mode1* pciclk4^ sdram 8 vssp 3v66-0 vdd48 pd#/reset$ sdata* sdclk* vddlapic ioapic vssc refx2/*fs3 cpuclk0 vddlcpu cpuclk1 vsss sdram 0 sdram 1 sdram 2 vdds sdram 3 vsss sdram 4 sdram 5 sdram 6 sdram 7 vssa vdds 48mhz_0 *sio_sel/24_48mhz pciclk5^ vdda vdd3 3v66-1 vddp pciclk1^/ fs1# 48mhz_1/ fs4# 3v66-2 vss *: internal pull - up #: active low $: ope drain 4.0 pin description in - input out - output i/o - bi - directional pin # - active low l - internal 250k w pull - up
w83194br - s preliminary publ ication release date: june 2000 - 3 - revision 0.42 4.1 crystal i/o symbol pin i/o function xin 3 in crystal input with internal loading capacitors(36pf) and feedback resistors. xout 4 out crystal output at 14.318mhz nominally with internal loading capacitors(36pf). 4.2 cpu, sdram, pci, ioapic clock outputs symbol pin i/o fu nction cpuclk [0:1] 45,44 out low skew (< 250ps) clock outputs for host frequencies such as cpu and chipset. pd#/reset$ 29 in pin16 *mode1=1, power down mode when driven low. pin16 *mode1=0, reset# output (4ms low active pulse when watch dog time out) ioapic 47 out clock outputs synchronous with pci clock and powered by vdda. sdram [ 0:8] 41,40, 39,37,36,35,33 ,32,31 out sdram clock outputs. pciclk0/ *fs0 11 i/o 3.3v 33mhz pci clock during normal operation. latched input for fs0 at initial power up for h/w selecting the output frequency of cpu, sdram and pci clocks(default=1). pciclk1/ fs1# 12 i/o low skew (< 250ps) pci clock outputs. latched input for fs1 at initial power up for h/w selecting the output frequency of cpu, sdram and pci clocks(default=0). pciclk2/ *fs2 13 i/o low skew (< 250ps) pci clock outputs. latched input for fs2 at initial power up for h/w selecting the output frequency of cpu, sdram and pci clocks(default=1). pciclk3/mode1* 15 i/o pci clock during normal operation. latched input. *mode1=1, pin 29 is pd#; *mode1=0, pin 29 is reset$ pciclk [ 4:6 ] 16,18,19 out low skew (< 250ps) pci clock outputs. 3v66 [0:2] 7,8,9 out 3.3v output clocks for the chipset.
w83194br - s preliminary publ ication release date: june 2000 - 4 - revision 0.42 4.3 i 2 c control interface symbol pin i/o function sdata 25 i/o serial data of i 2 c 2 - wire control interface sdclk 28 in serial clock of i 2 c 2 - wire control interface 4.4 fixed frequency outputs symbol pin i/o function refx2 / *fs3 3 i/o 14.318mhz reference clock. this ref output is the strong er buffer for isa bus loads. latched input for fs3 at initial power up for h/w selecting the output frequency of cpu, sdram and pci clocks (default=1). *sio_sel/24_48mhz 23 i/o 24mhz or 48mhz output clock. latched input for sio_sel at initial power up for the output frequency of 24mhz(high) and 48mhz(low) clocks. 48mhz_0 21 o 48mhz output for usb during normal operation. 48mhz_1/ fs4# 22 i/o 48mhz / latched input for fs4 at initial power up for h/w selecting the output frequency of cpu, sdram and pci clocks (default=0). 4.5 power pins symbol pin function vddl 48 power supply for cpu & ioapic, 2.5v or 3.3v. vdd48 24 power supply for 48mhz output,3.3v. vdd3 6 power supply for 3v_66 output, 3.3v. vddp 16 power supply for pciclk, 3.3v. vddr 2 power supply for refx2, 3.3v. vdds 42,34 power supply for sdram[0:8], nominal 3.3v. vdda 27 power for i2c clk and data. vss 5,10,14,20,26,30,38, 43 circuit ground.
w83194br - s preliminary publ ication release date: june 2000 - 5 - revision 0.42 5.0 frequency select ion by hardware fs4 fs3 fs2 fs1 fs0 cpu(mhz) sdram (mhz) 3v66(mhz) p ci(mhz) ioapic (mhz) 0 0 0 0 0 75.30 112.95 75.30 37.65 18.83 0 0 0 0 1 95.00 95.00 63.33 31.67 15.83 0 0 0 1 0 129.00 129.00 86.00 43.00 21.50 0 0 0 1 1 150.00 113.00 75.33 37.67 18.83 0 0 1 0 0 150.00 150.00 75.00 37.50 18.75 0 0 1 0 1 110.00 110.00 73.33 36.67 18.33 0 0 1 1 0 140.00 140.00 70.00 35.00 17.50 0 0 1 1 1 144.00 108.00 72.00 36.00 18.00 0 1 0 0 0 68.30 102.45 68.30 34.15 17.08 0 1 0 0 1 105.00 105.00 70.00 35.00 17.50 0 1 0 1 0 138. 00 138.00 69.00 34.50 17.25 0 1 0 1 1 140.00 105.00 70.00 35.00 17.50 0 1 1 0 0 66.80 100.20 66.80 33.40 16.70 0 1 1 0 1 100.20 100.20 66.80 33.40 16.70 0 1 1 1 0 133.60 133.60 66.80 33.40 16.70 0 1 1 1 1 133.60 100.20 66.80 33.40 16.70 1 0 0 0 0 157.30 118.00 78.67 39.33 19.67 1 0 0 0 1 160.00 120.00 80.00 40.00 20.00 1 0 0 1 0 146.00 110.00 73.33 36.67 18.33 1 0 0 1 1 122.00 91.50 61.00 30.50 15.25 1 0 1 0 0 127.00 127.00 84.67 42.33 21.17 1 0 1 0 1 122.00 122.00 81.33 40.67 20.33 1 0 1 1 0 117.00 117.00 78.00 39.00 19.50 1 0 1 1 1 114.00 114.00 76.00 38.00 19.00 1 1 0 0 0 80.00 120.00 80.00 40.00 20.00 1 1 0 0 1 78.00 117.00 78.00 39.00 19.50 1 1 0 1 0 166.00 166.00 83.00 41.50 20.75 1 1 0 1 1 160.00 160.00 80.00 40.00 20.00 1 1 1 0 0 66.60 100.00 66.67 33.33 16.67 1 1 1 0 1 100.00 100.00 66.67 33.33 16.67 1 1 1 1 0 133.30 133.30 66.65 33.33 16.66 1 1 1 1 1 133.30 100.00 66.67 33 .33 16.67
w83194br - s preliminary publ ication release date: june 2000 - 6 - revision 0.42 6.0 serial control registers the pin column lists the affected pin number and the @powerup column gives the state at true power up. registers are set to the values shown only on true power up. "command code" byte and "byte count" byte mu st be sent following the acknowledge of the address byte. although the data (bits) in these two bytes are considered "don't care", they must be sent and will be acknowledge. after that, the below described sequence (register 0, register 1, register 2, ....) will be valid and acknowledged. frequency table setting by i2c (sel5 ~ sel0) ssel5 ssel4 ssel3 ssel2 ssel1 ssel0 cpu (mhz) sdram (mhz) 3v66 (mhz) pci(mhz) ioapic (mhz) 0 0 0 0 0 0 75.30 112.95 75.30 37.65 18.83 0 0 0 0 0 1 95.00 95.00 63 .33 31.67 15.83 0 0 0 0 1 0 129.00 129.00 86.00 43.00 21.50 0 0 0 0 1 1 150.00 113.00 75.33 37.67 18.83 0 0 0 1 0 0 150.00 150.00 75.00 37.50 18.75 0 0 0 1 0 1 110.00 110.00 73.33 36.67 18.33 0 0 0 1 1 0 140.00 140.00 70.00 3 5.00 17.50 0 0 0 1 1 1 144.00 108.00 72.00 36.00 18.00 0 0 1 0 0 0 68.30 102.45 68.30 34.15 17.08 0 0 1 0 0 1 105.00 105.00 70.00 35.00 17.50 0 0 1 0 1 0 138.00 138.00 69.00 34.50 17.25 0 0 1 0 1 1 140.00 105.00 70.00 35.00 1 7.50 0 0 1 1 0 0 66.80 100.20 66.80 33.40 16.70 0 0 1 1 0 1 100.20 100.20 66.80 33.40 16.70 0 0 1 1 1 0 133.60 133.60 66.80 33.40 16.70 0 0 1 1 1 1 133.60 100.20 66.80 33.40 16.70 0 1 0 0 0 0 157.30 118.00 78.67 39.33 19.67 0 1 0 0 0 1 160.00 120.00 80.00 40.00 20.00 0 1 0 0 1 0 146.00 110.00 73.33 36.67 18.33 0 1 0 0 1 1 122.00 91.50 61.00 30.50 15.25 0 1 0 1 0 0 127.00 127.00 84.67 42.33 21.17 0 1 0 1 0 1 122.00 122.00 81.33 40.67 20.33 0 1 0 1 1 0 117.00 117.00 78.00 39.00 19.50 0 1 0 1 1 1 114.00 114.00 76.00 38.00 19.00 0 1 1 0 0 0 80.00 120.00 80.00 40.00 20.00 0 1 1 0 0 1 78.00 117.00 78.00 39.00 19.50 0 1 1 0 1 0 166.00 166.00 83.00 41.50 20.75 0 1 1 0 1 1 160 .00 160.00 80.00 40.00 20.00 0 1 1 1 0 0 66.60 100.00 66.67 33.33 16.67
w83194br - s preliminary publ ication release date: june 2000 - 7 - revision 0.42 0 1 1 1 0 1 100.00 100.00 66.67 33.33 16.67 0 1 1 1 1 0 133.30 133.30 66.65 33.33 16.66 0 1 1 1 1 1 133.30 100.00 66.67 33.33 16.67 ssel5 ssel4 ssel3 ssel 2 ssel1 ssel0 cpu (mhz) sdram (mhz) 3v66 (mhz) pci(mhz) ioapic (mhz) 1 0 0 0 0 0 136.00 102.00 68.00 34.00 17.00 1 0 0 0 0 1 138.00 138.00 69.00 34.50 17.25 1 0 0 0 1 0 139.00 104.25 69.50 34.75 17.38 1 0 0 0 1 1 141.00 105.75 70.50 35.25 17.63 1 0 0 1 0 0 142.00 142.00 71.00 35.50 17.75 1 0 0 1 0 1 142.00 106.50 71.00 35.50 17.75 1 0 0 1 1 0 143.00 143.00 71.50 35.75 17.88 1 0 0 1 1 1 143.00 107.25 71.50 35.75 17.88 1 0 1 0 0 0 144.00 144.00 72.00 36.0 0 18.00 1 0 1 0 0 1 144.00 108.00 72.00 36.00 18.00 1 0 1 0 1 0 146.00 146.00 73.00 36.50 18.25 1 0 1 0 1 1 146.00 109.50 73.00 36.50 18.25 1 0 1 1 0 0 147.00 147.00 73.50 36.75 18.38 1 0 1 1 0 1 147.00 110.25 73.50 36.75 18. 38 1 0 1 1 1 0 148.00 148.00 74.00 37.00 18.50 1 0 1 1 1 1 148.00 111.00 74.00 37.00 18.50 1 1 0 0 0 0 149.00 111.75 74.50 37.25 18.63 1 1 0 0 0 1 152.00 152.00 76.00 38.00 19.00 1 1 0 0 1 0 153.00 114.75 76.50 38.25 19.13 1 1 0 0 1 1 156.00 156.00 78.00 39.00 19.50 1 1 0 1 0 0 157.00 117.75 78.50 39.25 19.63 1 1 0 1 0 1 158.00 158.00 79.00 39.50 19.75 1 1 0 1 1 0 159.00 119.25 79.50 39.75 19.88 1 1 0 1 1 1 160.00 160.00 80.00 40.00 20.00 1 1 1 0 0 0 162.00 121.50 81.00 40.50 20.25 1 1 1 0 0 1 164.00 123.00 82.00 41.00 20.50 1 1 1 0 1 0 170.00 127.50 85.00 42.50 21.25 1 1 1 0 1 1 175.00 116.67 77.78 38.89 19.44 1 1 1 1 0 0 180.00 120.00 80.00 40.00 20.00 1 1 1 1 0 1 1 85.00 185.00 61.67 30.83 15.42 1 1 1 1 1 0 190.00 126.67 63.33 31.67 15.83 1 1 1 1 1 1 200.40 133.60 66.80 33.40 16.70
w83194br - s preliminary publ ication release date: june 2000 - 8 - revision 0.42 6.1 register 0: control register bit @powerup pin description 7 x - fs0# 6 x - fs1# 5 x - fs2# 4 x - fs3# 3 x - f s4# 2 1 - if reg0 - bit7=1 0 = 0.5% center type spread spectrum modulation 1 = 0.75% center type spread spectrum modulation if reg0 - bit7=0 0 = - 0.6 % down type spread spectrum modulation 1 = - 1.0% down type spread spectrum modulation 1 0 - 0 = norm al 1 = spread spectrum enabled 0 1 - 1=center spread 0=down spread 6.2 register 1 : sdram register (1 = active, 0 = inactive) bit @powerup pin description 7 1 38 sdram7 (active / inactive) 6 1 41 sdram6 (active / inactive) 5 1 42 sdram5 (active / in active) 4 1 43 sdram4 (active / inactive) 3 1 44 sdram3 (active / inactive) 2 1 47 sdram2 (active / inactive) 1 1 48 sdram1 (active / inactive) 0 1 49 sdram0 (active / inactive) 6.3 register 2: pci clock register (1 = active, 0 = inactive) bit @power up pin description 7 1 20 pciclk7 (active / inactive) 6 1 19 pciclk6 (active / inactive) 5 1 18 pciclk5 (active / inactive) 4 1 16 pciclk4 (active / inactive) 3 1 15 pciclk3 (active / inactive) 2 1 13 pciclk2 (active / inactive) 1 1 12 pciclk1 (act ive / inactive) 0 1 11 pciclk0 (active / inactive)
w83194br - s preliminary publ ication release date: june 2000 - 9 - revision 0.42 6.4 register 3: control register (1 = active, 0 = inactive) bit @powerup pin description 7 1 9 3v66_2(active/inactive) 6 1 8 3v66_1(active / inactive) 5 1 7 3v66_0(active / inactive) 4 1 23 24_48mhz (active / inactive) 3 1 47 ioapic (active / inactive) 2 1 21 48mhz0 (active / inactive) 1 1 22 48mhz1 (active / inactive) 0 1 1 ref2x (active / inactive) 6.5 register 4: control register (1 = active, 0 = inactive) bit @powerup pin description 7 0 - s sel3 (frequency table selection by software via i 2 c ) 6 0 - ssel2 ( frequency table selection by software via i 2 c) 5 0 - ssel1 ( frequency table selection by software via i 2 c) 4 0 - ssel0 ( frequency table selection by software via i 2 c) 3 0 - 0 = selec tion by hardware 1 = selection by software i 2 c - bit (1,2, 4:6) 2 0 - ssel4 (frequency table selection by software via i 2 c ) 1 0 - ssel5 (frequency table selection by software via i 2 c ) 0 0 - 0 = running 1 = tristate all outputs 6.6 register 5: skew r egister bit @powerup pin description 7 1 - cskew2 (cpu to sdram skew program bit) 6 0 - cskew1 (cpu to sdram skew program bit) 5 0 - cskew0 (cpu to sdram skew program bit) 4 1 - caskew2 (cpu to 3v66 skew program bit) 3 0 - caskew1 (cpu to 3v66 skew pr ogram bit) 2 0 - caskew0 (cpu to 3v66 skew program bit) 1 1 51 cpuclk1(active/inactive) 0 1 52 cpuclk0(active / inactive)
w83194br - s preliminary publ ication release date: june 2000 - 10 - revisio n 0.42 6.7 register 6~10: step - less m/n mode control registers 6.12 register 11: winbond chip id register (read only) bit @powerup pin description 7 0 - winbond chip id 6 1 - winbond chip id 5 0 - winbond chip id 4 1 - winbond chip id 3 0 - winbond chip id 2 0 - winbond chip id 1 0 - winbond chip id 0 0 - winbond chip id 6.13 register 12: winbond chip id register (read only) bit @powerup pin description 7 0 - winbond chip id 6 1 - winbond chip id 5 0 - winbond chip id 4 0 - winbond chip id 3 0 - winbond chip id 2 0 - winbond version id 1 1 - winbond version id 0 0 - winbond version id register10 bit3 - 6 ratio bit6 bit 5 bit 4 bit 3 ds3 ds2 ds1 ds0 cpu sdram 3v66 0 0 0 0 4 4 6 0 0 0 1 3 3 6 0 0 1 0 2 3 6 0 0 1 1 2 2 6 0 1 0 0 6 4 6 0 1 0 1 3 4 6 0 1 1 0 6 3 6 0 1 1 1 4 3 6 1 0 x x 2 2 4 1 1 x x 2 4 6
w83194br - s preliminary publ ication release date: june 2000 - 11 - revisio n 0.42 7.0 specifications 7.1 absolute maximum ratings stresses greater than those listed in this table may cause permanent damage to the device. precautions should be taken to avoid application of any voltage higher than the maximum rated voltages to this circuit. maximum conditions for extended periods may affect rel iability. unused inputs must always be tied to an appropriate logic voltage level (ground or vdd). symbol parameter rating vdd , v in voltage on any pin with respect to gnd - 0.5 v to + 7.0 v t stg storage temperature - 65 c to + 150 c t b ambient tempe rature - 55 c to + 125 c t a operating temperature 0 c to + 70 c 7.2 electronical characteristics --- input/output vddq1=vddq2 = vddq3 = vddq4 =3.3v, vddl1 =vddl2= 2.5v , t a = 0 c to +70 c parameter symbol min typ max units test conditions input low vo ltage v il vss - 0.3 0.8 v dc input high voltage v ih 2.0 vdd+0.3 v dc input low current i il - 5 m a no pull - up resistors input low current i il - 200 m a pull - up resistros input high current i ih - 5 5 m a input capacitance c in 5 pf logic inputs c out 6 pf output capacitance c inx 27 45 pf xin and xout operating supply current i dd3 100 ma cpu = 66.6 mhz pci = 33.3 mhz with load power down supply current i dd2 600 m a settling time ts 3 ms from first crossing to 1% target freq.
w83194br - s preliminary publ ication release date: june 2000 - 12 - revisio n 0.42 delay t pzh ,t pzh 1 10 ns output enable delay t plz ,t pzh 1 10 ns output enable delay 7.3 electronical characteristics of cpu clock vdd=2.5v +/ - 5%; c l =10 - 20pf parameter symbol min typ max units test conditions ouput impedance r dsp 13.5 40 ohm ouput impeda nce r dsn 13.5 40 ohm output low voltage v ol 0.4 v i ol =1ma output high voltage v oh 2.0 v i oh = - 1ma output low current i ol 27 30 ma output high current i oh - 27 - 27 ma pull - up current min i oh(min) - 27 ma vout = 1.0 v pull - up current max i oh(m ax) - 27 ma vout = 2.0v rise/fall time min between 0.4 v and 2.0 v t rf(min) 0.4 ns 10pf load rise/fall time max between 0.4 v and 2.0 v t rf(max) 1.6 ns 20pf load duty cycle dt 45 55 % v t =1.25v skew t sk 175 ps v t =1.25v jitter tsc - c 250 ps v t = 1.25v 7.4 electronical characteristics of 3v66 clock vdd=3.3v +/ - 5%; c l =10 - 30pf parameter symbol min typ max units test conditions ouput impedance r dsp 15 55 ohm ouput impedance r dsn 15 55 ohm output low voltage v ol 0.55 v i ol =1ma output high voltage v oh 2.4 v i oh = - 1ma output low current i ol 30 38 ma output high current i oh - 33 - 33 ma rise/fall time min between 0.4 v and 2.0 v t rf(min) 0.4 ns 10pf load rise/fall time max between 0.4 v and 2.0 v t rf(max) 1.6 ns 20pf load
w83194br - s preliminary publ ication release date: june 2000 - 13 - revisio n 0.42 duty cycl e dt 45 55 % v t =1.5v skew t sk 175 ps v t =1.5v jitter tsc - c 500 ps v t =1.5v 7.5 electronical characteristics of sdram clock vdd=3.3v +/ - 5%; c l =20 - 30pf parameter symbol min typ max units test conditions ouput impedance r dsp 13.5 40 ohm ouput imp edance r dsn 13.5 40 ohm output low voltage v ol 0.45 v i ol =1ma output high voltage v oh 2.4 v i oh = - 1ma output low current i ol 54 54 ma output high current i oh - 54 - 45 ma rise/fall time min between 0.4 v and 2.0 v t rf(min) 0.4 ns 10pf load r ise/fall time max between 0.4 v and 2.0 v t rf(max) 1.6 ns 20pf load duty cycle dt 45 55 % v t =1.5v skew t sk 250 ps v t =1.5v jitter tsc - c 250 ps v t =1.5v 7.6 electronical characteristics of pci clock vdd=3.3v +/ - 5%; c l =10 - 30pf parameter symbol mi n typ max units test conditions ouput impedance r dsp 15 55 ohm ouput impedance r dsn 15 55 ohm output low voltage v ol 0.55 v i ol =1ma output high voltage v oh 2.4 v i oh = - 1ma output low current i ol 30 38 ma output high current i oh - 33 - 33 ma rise/fall time min between 0.4 v and 2.0 v t rf(min) 0.5 ns 10pf load rise/fall time max between 0.4 v and 2.0 v t rf(max) 2.0 ns 20pf load
w83194br - s preliminary publ ication release date: june 2000 - 14 - revisio n 0.42 between 0.4 v and 2.0 v duty cycle dt 45 55 % v t =1.5v skew t sk 500 ps v t =1.5v jitter tsc - c 500 ps v t =1.5v 7.7 electronical cha racteristics of 48mhz, ref clock vdd=3.3v +/ - 5%; c l =10 - 20pf parameter symbol min typ max units test conditions ouput impedance r dsp 20 55 ohm ouput impedance r dsn 20 55 ohm output low voltage v ol 0.4 v i ol =1ma output high voltage v oh 2.4 v i oh = - 1ma output low current i ol 29 27 ma output high current i oh - 29 - 23 ma risetime t r 1.8 4 ns 10pf load fall time t f 1.7 4 ns 20pf load duty cycle dt 45 55 % v t =1.5v skew t sk 500 ps v t =1.5v jitter tsc - c 1000 ps v t =1.5v
w83194br - s preliminary publ ication release date: june 2000 - 15 - revisio n 0.42 8.0 or dering information part number package type production flow w83194br - s 48 pin ssop commercial, 0 c to +70 c 9.0 how to read the top marking 1st line: winbond logo and the type number: w83194br - s 2nd line: tracking code 2 8051234 2 : wa fers manufactured in winbond fab 2 8051234 : wafer production series lot number 3rd line: tracking code 814 g b b 814 : packages made in ' 98 , week 14 g : assembly house id; o means ose, g means gr a : internal use code b : ic revision all the trade marks of products and companies mentioned in this data sheet belong to their respective owners . w83194br - s 28051234 814gab
w83194br - s preliminary publ ication release date: june 2000 - 16 - revisio n 0.42
w83194br - s preliminary publ ication release date: june 2000 - 17 - revisio n 0.42 10.0 package drawin g and dimensions headquarters no. 4, creation rd. iii science-based industrial park hsinchu, taiwan tel: 886-35-770066 fax: 886-35-789467 www: http://www.winbond.com.tw/ taipei office 11f, no. 115, sec. 3, min-sheng east rd. taipei, taiwan tel: 886-2-7190505 fax: 886-2-7197502 tlx: 16485 wintpe winbond electronics (h.k.) ltd. rm. 803, world trade square, tower ii 123 hoi bun rd., kwun tong kowloon, hong kong tel: 852-27516023-7 fax: 852-27552064 winbond electronics (north america) corp. 2730 orchard parkway san jose, ca 95134 u.s.a. tel: 1-408-9436666 fax: 1-408-9436668 please note that all data and specifications are subject to change without notice. all the tra de marks of products and companies mentioned in this data sheet belong to their respective owners . these products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to re sult in personal injury. winbond customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify winbond for any damages resulting from such improper use or sale.

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